1. Field of the Invention
This invention relates to a solid-state imaging device and a method of manufacturing the same, and more particularly to the structure of a semiconductor substrate and the structure of a dicing region in a CMOS amplification-type solid-state imaging device which is used in, for example, a digital camera.
2. Description of the Related Art
The advantage of a CMOS amplification-type solid-state imaging device (hereinafter, referred to as a CMOS image sensor) is a single power supply which operates at a low voltage of, for example, about 3 V and consumes low power, for example, about 50 mW of electric power. In the device, a plurality of pixels each included of a photoelectric conversion element and a plurality of transistors have been formed on a semiconductor substrate, thereby achieving a multi-pixel configuration. Each pixel has an amplifying function whereby the potential in a signal charge accumulating part is modulated by the signal charge generated by the photoelectric conversion element and the amplifying transistor in the pixel is modulated according to the modulated potential.
In a conventional CMOS image sensor, a p/p+ substrate is used as a semiconductor substrate. In the p/p+ substrate, a p-type epitaxial layer whose impurity concentration is low is formed to a thickness of about 5 to 10 μm on the surface of a p+-type substrate whose impurity concentration is high is used a semiconductor substrate. The reason why the p/p+ substrate is used is that the lifetime of carriers (electrons) is short in a part (p+-type substrate) where the impurity concentration is high in a deep position of the substrate. Specifically, even when a photo diode acting as a photoelectric conversion element is exposed to intense light, generating carriers, which diffuse deeply in the substrate, electrons recombine in a region where the lifetime of carriers is short. Accordingly, carriers overflowed from the photo diode as a result of the exposure of the photo diode to intense light or carriers generated by photoelectric conversion in a deep position of the substrate can be constrained from entering an adjacent photo diode. Therefore, the occurrence of blooming can be suppressed.
Furthermore, with the recent miniaturization of elements, the area of a photo diode is decreased, which causes the problem of deteriorating the sensitivity. The CMOS image sensor is characterized by low-voltage driving. Accordingly, it is difficult to broaden the depletion layer. Therefore, a decrease in the sensitivity resulting from the miniaturization of elements is difficult to compensate for by improving the sensitivity by broadening the depletion layer. To improve the sensitivity of the CMOS image sensor, it is important to use such a substrate structure as can gather carriers efficiently in the photo diode. For this reason, the p/p+ substrate is used. Specifically, in the p/p+ substrate, a region where the B (boron) concentration is low exists in a shallow position of the substrate at the surface of the substrate and a region where the boron concentration is high exists in a deep position of the substrate. As a result, the p/p+ substrate has an interface where the boron concentration changes rapidly. Then, even if electrons generated by photoelectric conversion try to diffuse into a deep place of the substrate, they bounce back from the interface where the boron concentration changes abruptly toward the surface of the substrate. Part of the bounced electrons gather at the photo diode exposed to light as a result of diffusion or the like, which improves the sensitivity.
To make a CMOS image sensor higher in pixel density in the future, not only has technical development to increase sensitivity become an important subject, but also the technique for suppressing the deterioration of picture quality, such as blooming or color mixture, has been desired.
A solid-state imaging device which uses an n/p+ substrate as a substrate structure capable of overcoming both of the two technical problems has been disclosed in the U.S. patent specification by the inventors related to US 2006/0219867 filed on Mar. 30, 2006 by the assignor and laid open on Oct. 5, 2006. The n/p+ substrate has a structure where an n-type semiconductor layer has been deposited on a p+-type substrate by the epitaxial growth method. When phosphorus ion-implanted in the n-type semiconductor layer (hereinafter, referred to as the n-type epitaxial layer) deposited by the epitaxial growth method to form an n-type semiconductor layer of a photo diode, the depletion layer of the photo diode extends more easily than when the p/p+ substrate is used. Therefore, carriers can be gathered efficiently in the photo diode, improving the sensitivity. Moreover, the shortness of the lifetime of carriers can be made use of, which enables the deterioration of image quality, such as blooming or light mixture, to be suppressed.
When CMOS image sensors are formed using the n/p+ substrate, there are several points to keep in mind. A first point to keep in mind is the element isolation between a plurality of photo diodes. In the n/p+ substrate, since the n-type semiconductor layer of a photo diode is formed in the n-type epitaxial layer, the photo diodes would be electrically connected to each other if they were left as they were. A second point to keep in mind is that a p-n junction surface appears at the dicing surface of the chip. The interface between the p+-type substrate and the n-type epitaxial layer, that is, a p-n junction surface, appears at the cut surface of the device chips diced along the dicing lines from a Si wafer in which a plurality of CMOS image sensors have been formed. When a p-n junction surface appears at the chip cut surface, the surface of the cutting plane becomes the cause of the occurrence of leakage current or is at high risk of acting as a flow channel of leakage current. Eventually, the possibility of increasing the leakage current will get greater.
The specification of the US 2006/0219867 has disclosed that a p-type semiconductor region has been formed in an element isolating region enclosing each photo diode in a plane and in a dicing region by implanting, for example, boron ions. Since boron ions are diffused from the p+-type substrate toward the n-type epitaxial layer in a heat treatment process or the like when the p-type semiconductor region is formed, a p-type semiconductor region is formed continuously by a p-type semiconductor region produced by boron ion implantation and boron diffusion from the p+-type base substrate.
When boron impurities are diffused from the p+-type substrate toward the n-type epitaxial layer, a part of the n-type epitaxial layer left without boron diffusion becomes a region where a photo diode is to be formed. Since the depth of the photo diode varies according to a subtle change in the heat history, there is a possibility that a variation in the sensitivity will become larger. Moreover, the deepest site of the photo diode in the depth direction (the tip in the depth direction) is determined by the limit of the acceleration of boron ions implantation in forming a p-type semiconductor region. For this reason, the number of carriers is restricted and therefore the sensitivity is limited.